Wafer Fabrication
The GDSII file from tapeout is a geometric description of every mask layer in the design. The foundry turns that into working silicon by repeating a core cycle — lithography, deposition, etch, doping — for every one of the design's metal and device layers, sometimes 100 or more lithography steps for a single modern chip, before the finished wafer is tested and diced into individual die.
Every metal and device layer goes through the same lithography → deposition → etch → doping/anneal cycle, planarized between layers by chemical-mechanical polishing (CMP). Once complete, the wafer is tested die-by-die before it's diced and packaged.
| Process step | What it does |
|---|---|
| Lithography | Projects a mask pattern onto photoresist using UV light, defining where the next process step will act |
| Deposition | Grows or coats a material onto the wafer (PVD, CVD, ALD, electrochemical deposition) to form the next layer |
| Etch | Removes material according to the lithography pattern (wet or dry etch), physically forming the layer's geometry |
| Doping | Implants dopant ions into source/drain regions, followed by annealing to activate them and repair implant damage |
| CMP (Chemical-Mechanical Polishing) | Planarizes the wafer surface between layers so the next lithography step has a flat, in-focus surface to pattern |
Process Corners
No two transistors come out of the fab identical — gate length, dopant concentration, and oxide thickness all vary slightly from die to die and wafer to wafer, and that variation directly changes how fast or slow a transistor switches. Rather than simulate every possible real value, timing signoff instead checks the design against a handful of deliberately extreme "corner" models that are meant to bound the real distribution: if the design works at the extremes, it should work everywhere in between.
The first letter of a corner name is NMOS speed, the second is PMOS speed. TT/FF/SS sit on the diagonal where NMOS and PMOS vary together; FS/SF are skewed corners used to stress designs sensitive to a rise/fall imbalance. Voltage and temperature add two more axes on top of this process axis — together, process + voltage + temperature form the full "PVT" corner space.
| Corner | Typically used for |
|---|---|
| SS + low voltage + high temperature | Worst case for setup timing — the slowest the design will ever legitimately run |
| FF + high voltage + low temperature | Worst case for hold timing — the fastest the design will ever legitimately run, where hold violations are hardest to avoid |
| TT + nominal voltage + nominal temperature | Typical-case power and performance estimation — what a "normal" die is expected to look like |
| FS / SF (skewed) | Stress-testing paths sensitive to a mismatch between NMOS and PMOS drive strength, not just overall speed |
How a fab decides which corner a real die landed in
Corners are a design-time modeling abstraction — real fabricated die don't literally sort into five discrete buckets, they land somewhere on a continuous distribution. To find out where a given die actually sits, foundries place Process Control Monitor (PCM) structures — test transistors and ring oscillators — at fixed locations across every wafer, outside the die area or in scribe lines between die. After fabrication, these structures are measured directly: a ring oscillator's frequency (or a test transistor's drive current) reveals the real NMOS and PMOS speed for silicon in that specific location, which is then compared against the corner models used at signoff to say, in effect, "this region of this wafer behaves close to the FF corner" or "close to SS." That measurement is what actually drives both binning (Stage 12's post-silicon section below) and yield learning — feeding real process data back to the fab so the next lot can be centered more tightly around the intended typical corner.
On-Chip Variation & Sigma
Process corners bound die-to-die variation, but there's a second, finer-grained effect: even within one single die, no two nominally identical transistors are perfectly identical either — this is on-chip variation (OCV). Because a real chip has millions of instances of the "same" cell, their behavior isn't one number but a distribution, and modern signoff models that distribution statistically rather than assuming every instance is simultaneously at its absolute worst.
Parametric On-Chip Variation (POCV) models each gate's delay as a mean plus a standard deviation (sigma) instead of one worst-case number, then signs off at a chosen sigma point (commonly 3σ, ≈99.7% coverage) rather than an unrealistic all-instances-simultaneously-worst-case assumption.
| Variation type | Behavior |
|---|---|
| Global variation | Correlated across the whole die (or wafer) — shifts the entire delay distribution up or down together; grows roughly linearly with path length since every stage along a path is affected the same way |
| Local (random) variation | Uncorrelated, instance-to-instance — widens the distribution rather than shifting it; grows roughly with the square root of path length, since independent random effects partially average out over a long path |
Older OCV methodology applied a single flat derate to every path regardless of its actual composition; AOCV (advanced OCV) improved on that by varying the derate with logic depth and physical distance; POCV (parametric OCV), now the common modern approach, goes further and computes arrival and required times statistically from each cell's own characterized mean/sigma, which removes a large amount of the pessimism a flat derate would otherwise bake in — directly analogous to the Sigma-AV/Sigma-DVD statistical approach used for power integrity (see EMIR Analysis), applied here to timing instead of voltage.
Yield
Yield is simply the fraction of manufactured die that come out good — functionally correct and meeting spec — out of everything put on the wafer. It's the single number that connects design decisions all the way back to cost: a larger, denser die catches more random defects per unit area, so bigger chips have structurally lower yield than smaller ones at the same defect density, all else equal.
A wafer map plots pass/fail per die location. Real defects cluster (particles, edge effects, localized process excursions) rather than spreading uniformly at random.
D₀ is defect density (average fatal defects per unit area) and Acrit is the die's critical area — the layout area sensitive enough to a given defect size to actually cause a failure. Murphy's model assumes defect density itself varies across the wafer (rather than being perfectly uniform, the way a plain Poisson model assumes), which better matches real fabs where defects cluster — and it typically predicts lower yield than plain Poisson for the same D₀ and die size as a result.
| Yield type | What it measures |
|---|---|
| Die yield / functional yield | Fraction of die that pass functional and parametric test at wafer sort |
| Parametric yield | Fraction of die meeting analog/timing/power specs, independent of pure logical correctness — a die can be functionally correct but too slow or too leaky to bin acceptably |
| Test yield / package yield | Fraction of already-good die that survive packaging and final test without new defects introduced by assembly |
Improving Yield
Yield improvement happens on both sides of the fab/design boundary — the fab tightens its own process control, and the design is made deliberately more tolerant of the variation and defects that remain.
| Technique | How it helps |
|---|---|
| Design-for-Manufacturability (DFM) checks | Lithography-simulation, CMP-simulation, and critical-area analysis run against the layout to flag geometries that are statistically fragile before tapeout, not after |
| Redundancy & repair | Spare rows/columns in memories (see MBIST & Memory Testing's BIRA/BISR) let a die with a localized defect still ship instead of being scrapped outright |
| Critical-area reduction | Wider wire spacing, via doubling, and more regular layout patterns shrink the area that's actually sensitive to a given defect size, directly lowering Acrit in the yield formula |
| Statistical (not flat worst-case) margining | POCV-based timing signoff (previous section) avoids over-designing against a scenario that's vanishingly unlikely to actually occur, which otherwise wastes area/power chasing margin that doesn't improve real yield |
| Binning | Parts that don't meet the top speed/power grade but still work correctly at a lower grade are sold into that lower bin instead of being scrapped — recovering value from parametric, not just catastrophic, variation |
| Yield learning loop | Inline metrology and wafer-map defect data are fed back to the fab line to find and fix the dominant defect mechanism of the moment — this is why yield on a given process node climbs steadily from initial risk production toward its mature-node ceiling over time |
Post-Silicon Bring-Up & ATPG
Everything up to this point has been preparation. This section covers what actually happens once wafers come back from the fab: the structural ATPG test every single die gets before it can ship, and the separate, much deeper characterization and debug work done on the first handful of parts to confirm the design itself is correct.
First silicon goes through bring-up and deep characterization once; every subsequent die only ever sees the fast structural ATPG pass at wafer sort and final test, plus qualification screening for parts that need it.
What ATPG actually runs once chips come back
The scan and MBIST patterns generated back in Scan & ATPG and MBIST are what actually run here — first-silicon bring-up doesn't invent new test content, it's where those patterns get applied to real physical die for the first time and validated against the tester. Typical structural content run at this stage: stuck-at scan patterns (the DC baseline), at-speed transition patterns (run at the part's real target frequency), MBIST algorithms against every embedded memory, and boundary-scan/JTAG interconnect checks. All of it runs on Automatic Test Equipment (ATE) — first at wafer sort (probing the still-unpackaged die), then again at final test after packaging.
Characterization: proving the design across the full corner space
Where production ATPG just asks pass/fail, characterization on first silicon asks a much bigger question: does the design actually work everywhere the process corners and OCV/sigma analysis claimed it should? This is done with shmoo plots — sweeping two parameters at once (commonly voltage and frequency) and plotting pass/fail at every combination, which quickly shows whether the part's real operating margin matches what signoff predicted. "Corner lot" wafers are deliberately processed to skew toward the FF/SS/FS/SF extremes so engineers can test actual fast and slow silicon directly, not just typical die, and confirm the design tolerates the real variation those corner models were meant to represent.
Debug, qualification, and ramp
When a die fails, the same DFT structures built for production test become the debug tool: a scan dump captures the exact internal state at the point of failure, and JTAG gives direct register/memory access to isolate whether the failure is a design bug, a specific manufacturing defect, or a test-program problem. Parts destined for high-reliability or automotive use typically also go through burn-in — running at elevated voltage and temperature for an extended period to force early-life ("infant mortality") defects to fail before shipment rather than in the field. Once first silicon is debugged and characterized, the design moves into volume production, where every die only ever sees the fast structural ATPG pass, and yield/coverage data continues feeding back into the yield-learning loop described above.
Sources
General industry research plus IEEE Xplore literature — this page is not sourced from vendor-specific internal documentation.
- Photolithography (Lithography) — Semiconductor Microchips and Fabrication — Wiley-IEEE Press / IEEE Xplore
- CMOS Technology: Present and Future — IEEE Xplore
- A Fast Approach for Static Timing Analysis Covering All PVT Corners — IEEE Xplore
- A Parametric Approach for Handling Local Variation Effects in Timing Analysis (POCV) — IEEE Xplore
- A New Generation of Static Timing Analysis Technology Based on N7+ Process — POCV — IEEE Xplore
- Yield Analysis by Poisson Yield Model Based on the Defect Analysis with Derivative Method — IEEE Xplore
- Lithography-Aware Critical Area Estimation and Yield Analysis — IEEE Xplore
- Yield Modeling and Analysis — Prof. Robert C. Leachman, UC Berkeley
- Recent Trends on Post-Silicon Validation and Debug: An Overview — IEEE Xplore
- Shmoo Plotting: The Black Art of IC Testing — IEEE Xplore
- Automatic Test Pattern Generation in VLSI — A Survey — IEEE Xplore