The One Question That Decides The Type
In a single cycle of the cell's clock(s), can the array do more than one operation? Everything else — how it's named, how it's characterized, how it's used — follows from the answer.
| Type | Clocks | RTL ports | Bitcell ports | Same cycle: read | Same cycle: write | Same cycle: read & write |
|---|---|---|---|---|---|---|
| 1P SRAM | 1 — CLK |
1 address / 1 data | 1 | yes (instead of write) | yes (instead of read) | no |
| True 2-Port | 2 — CLKA, CLKB |
2 independent | 2 | yes on a port | yes on a port | yes — one port each, or both |
| Pseudo 2-Port | 1 — CLK |
2 (separate R and W pins) | 1 | yes | yes | not truly — R then W on the same clock |
| TCAM | 1 — CLK |
1 + compare bus | 1 (+ match lines) | yes (table access) | yes (update entry) | no — compare or R/W, not both |
| ROM | 1 — CLK |
1 address / 1 data-out | 1 (mask / via bits) | yes | no | no |
The Five Types At A Glance
1-Port SRAM
One clock, one address. The cycle is either a read or a write.
True 2-Port
Two clocks, two ports. Read on A and write on B in the same cycle is legal.
Pseudo 2-Port
Looks like 2P in RTL. One clock. Internally read-then-write (or write-then-read).
TCAM
The expensive cycle is compare: every entry is searched in parallel.
ROM
Bits are via- or mask-programmed. Functional cycles are read only.
Each type reduces to how many physical bitcell ports it has and how many clocks drive them — that alone determines what can happen in one cycle.
1-Port SRAM
A 1P SRAM has one clock and one address port. In any given cycle the controller asserts either a read enable or a write enable. The bitcell is opened once: you cannot read the old value and write a new value to the same (or another) word in that same cycle on this port.
What a cycle can be:
- Read — wordline up, bitlines develop, sense amps fire, data out.
- Write — wordline up, bitline drivers force the new bits. Often the higher-current of the two.
- Standby / idle — clock may still run; array is not accessed. Leakage plus a small clock-tree / decoder current.
A mix such as "half the cycles read, half write" is a statistical description across many cycles — not both operations inside one cycle.
One clock, one bitcell port — every cycle is exactly one of read, write, or idle, never a mix.
Compiler names: SAS*, SAC*, SAD* when they are not also ULS/RLS/TCS 2P; also …ULS…1P*, …RLS…1P*, SADULS*, SASSLS*, SADCLS*. ULS + 1P is still 1P. Same for RLS + 1P.
True 2-Port (Register File / Dual-Port SRAM)
A true 2-port has two physical access paths into the array and usually two clocks: CLKA for port A and CLKB for port B. The clocks may be the same frequency and aligned, or independent. Each port has its own address and its own read/write control.
In one cycle of both clocks (when they coincide), the cell can:
- Read on A, write on B
- Write on A, read on B
- Read on both (if the compiler allows 2R)
- Write on both (if the compiler allows 2W — watch same-address collisions)
That simultaneous pair is the read_write (dual-port) mode — the operation 1P and pseudo 2-port cannot do. Current is roughly "a read plus a write" in the same window, on two clock pins.
Two independent bitcell ports, two clocks — port A and port B can each read or write in the same cycle, independently.
Compiler names: RLS plus 2P — SACRLS0G4S2P*, SACRLS0G4L2P*, SACRLS0G4U2P*, SASRLS0G0*2P*. The letter before 2P (S / L / U) is a speed / leakage bin, not a different type.
Pseudo 2-Port
Pseudo 2-port is the type people confuse with true 2-port. The RTL wrapper exposes a read address and a write address so the block can issue both in the same architectural cycle. The silicon is still a 1-port bitcell array with one clock (CLK). There is no CLKA / CLKB.
What actually happens in that one clock:
- The internal mux gives the bitcell to the write (or the read) first.
- Then it gives the bitcell to the other operation.
- From outside it looks like "I read and wrote this cycle." Inside it is two half-operations back to back, not two ports at once.
That is why the characterized mode is often called pwl_read_write (piecewise-linear read-then-write on one clock) or a mode sequence read → write → read → write. Same hardware idea: one clock, two steps, never a true dual-port current peak.
The RTL view (top) looks like simultaneous read+write every cycle; inside the array (bottom) it's always sequenced — one clock, two steps.
Compiler names: ULS plus 2P — SACULS0G4L2P*, SACULS0G4U2P*, SASULS0G4U2P*. SACULS0G4L1P* is not this type — that cell is a 1P SRAM from the same ULS compiler.
TCAM
A ternary CAM stores bits that can be 0, 1, or X (don't care). The cycle that makes it a CAM is compare / search: the compare bus is driven onto every word in parallel, match lines fire, a hit (or a list of hits) comes out. That is not a SRAM read — many more wordlines / match lines switch, so compare is the high-current mode.
A TCAM still has ordinary read and write so software can install or dump entries. Those are 1-port table accesses. In one clock you do one of:
- Compare (search)
- Read an entry
- Write / update an entry
You do not compare and write the table in the same cycle. One clock (CLK).
Compare dominates a TCAM's cycle mix; table read/write are occasional, lower-current 1-port accesses interleaved with it.
Compiler names: TCS (for example SADTCS0G4L1P*) and SAHT* (hash / CAM family on some nodes).
ROM
A via-ROM or mask-ROM has the bits built into the metals / vias. There is no functional write. One clock, one address, data out. The only real operating mode is read. Standby is just "not reading."
No write mode exists at all — a ROM cycle is either a read or idle.
Compiler names: ASD*, ASDVD*. These show up far less often in block cell lists than SRAMs.
Operating Modes, In Detail
A "mode" is one characterized way the cell draws current for one cycle (or one sequenced pair of steps). The names below are the usual library / AVM names.
| Mode | What the silicon does in that step | Legal on | Same-cycle pairing |
|---|---|---|---|
read / avm_read |
One wordline, sense. Data out. | 1P, 2-port (per port), p2p (as one step), TCAM (table read), ROM | Alone on 1P / ROM / TCAM. On true 2-port it can sit next to a write on the other port. |
write / avm_write |
One wordline, bitline drivers force new data. | 1P, 2-port, p2p (as one step), TCAM (update) | Alone on 1P / TCAM. Never on ROM. On true 2-port it can sit next to a read on the other port. |
standby / standby_trig |
No array access. Clock / trigger logic may still toggle. | 1P (sometimes used as a third probability) | Not an access. Used to describe idle cycles in a mix. |
read_write / avm_read_write |
Both ports alive in the same instant: a read and a write overlapping. | True 2-port only | This is the same-cycle R+W. Illegal on ULS 2P or 1P — those cells have no such state. |
pwl_read_write |
One clock. A piecewise waveform: read current, then write current (or the reverse), still one CLK edge. |
Pseudo 2-port only | Looks like R+W to RTL. Internally two steps. Not the same current shape as true read_write. |
mode_sequence [read, write] |
Same p2p idea, told as an explicit loop: cycle N = read, cycle N+1 = write, repeat. Or two phases inside one clock if the period is set to a half-cycle. | Pseudo 2-port | Do not combine with pwl_read_write on the same cell — pick one description. |
compare / avm_compare |
Search key vs. every entry. Match lines. Highest TCAM current. | TCAM only | Not combined with a table write in the same cycle. |
How The Modes Look Over Time
Each row's current shape follows directly from its port/clock count — 2P alone shows two independent teeth per cycle; everything else shows one.
Probabilities Are Across Cycles
read = 0.5, write = 0.5 on a 1P means: over a long run, about half the accessed cycles look like a read and half like a write. It does not mean the cell reads and writes in one cycle. Adding standby = 0.5 with read 0.3 / write 0.2 means half the cycles do not access the array at all.
Sequence / PWL Is Inside The Cycle (P2P)
On a pseudo 2-port the library either publishes one PWL shape (read piece + write piece under one CLK) or you spell the two pieces as a sequence. Either way there is still only one clock pin. The current peak is usually lower and wider than a true 2-port read_write.
How To Read A Cell Name
The compiler packs the type into the name. The first 1P / 2P that sits in front of the size (272X55) is the port field. A later C1P0 in the tail is mux/bank config, not a port count.
| Token | With 1P | With 2P |
|---|---|---|
ULS | 1-port SRAM (one CLK, R or W) | pseudo 2-port (one CLK, R then W) |
RLS | 1-port SRAM | true 2-port (CLKA + CLKB, R and W) |
TCS / SAHT | TCAM (compare or R/W) | — treat as TCAM if you ever see it |
ASD | ROM (read only) | — |
plain SAS / SAC / SAD | 1-port SRAM | look at RLS / ULS before assuming 1P |
SACULS0G4L1P* is 1P. SACULS0G4L2P* is pseudo 2-port. SACRLS0G4L1P* is 1P. SACRLS0G4U2P* is true 2-port.
Cheatsheet
type clocks same-cycle access typical name
--------------------------------------------------------------------------------
1P SRAM CLK READ or WRITE SAS* SAC* SAD* *1P*
true 2-port CLKA,CLKB READ and WRITE (two ports) *RLS*2P*
pseudo 2-port CLK READ then WRITE (one port) *ULS*2P*
TCAM CLK COMPARE or READ or WRITE *TCS* SAHT*
ROM CLK READ ASD* ASDVD*
modes
read / avm_read single-port or per-port read
write / avm_write single-port or per-port write
standby / standby_trig no array access
read_write / avm_read_write true 2-port only -- both ports at once
pwl_read_write pseudo 2-port only -- R then W on CLK
sequence [read, write] same as p2p, spelled out
compare / avm_compare TCAM search