Overview
A power-delivery network (PDN) is the complex chain of interconnect — regulator, board, package, and on-die metal — that delivers current from the source to every transistor. As process nodes shrink, wire widths shrink and resistance rises, making supply voltage drop and noise one of the most critical signoff concerns in modern chip design.
Power integrity is increasingly treated as a chip-package-system (CPS) problem: accurately assessing PI requires modeling the electrical interaction between the die, the package, and the board together, not the chip in isolation.
Power Delivery Network (PDN)
Simplified on-die PDN: a peripheral power ring and cross-die straps carry bulk current at low resistance; fine-grain rails (zoomed) deliver current directly to each standard-cell row.
The PDN is a hierarchical grid of metal layers connected by vias, distributing power from package pins/bumps down to individual standard cells. It typically consists of:
Rings & Straps
Wide upper-metal power rings around the core and straps running across the die to carry bulk current with low resistance.
Rails
Fine-grain lower-metal power rails that run alongside standard cell rows, delivering current to individual gates.
IR Drop
IR drop is the voltage loss that occurs as current flows through the resistive PDN. When the voltage at a cell's supply pin falls below its expected level, the cell's drive strength and switching speed degrade, which can miss timing or switching thresholds and potentially cause functional failure. IR drop analysis is considered the most critical part of power integrity signoff.
A cell far from the source sees the accumulated drop of every segment along its path — which is why cells in the middle of a large block, farthest from the power ring, are typically the worst IR-drop offenders.
Left: voltage sags (blue → red) with distance from the power source across the die. Right: the same sag plotted as voltage vs. distance — cells farthest from the source risk dropping below the minimum functional voltage.
Static IR Drop
Caused by average voltage deviation across the resistive power grid under steady-state current draw. Easier to compute, used for early and broad signoff checks.
Dynamic IR Drop
Caused by localized, time-varying switching activity and current surges. Requires time-domain analysis that models grid resistance, capacitance, and inductance together with switching current sources — a more accurate but more expensive analysis.
Decoupling Capacitors (Decaps)
A decoupling capacitor (decap) is placed as a small local charge reservoir directly at or near a standard cell's supply pins. When a gate switches, it draws a burst of current; without a nearby decap, that current has to travel all the way back through the resistive/inductive PDN to the source, sagging the local supply. With a decap in parallel, most of that instantaneous current is supplied locally, so the rail barely moves.
Without a nearby decap, switching current must travel back through the resistive PDN, sagging the local VDD/VSS rails at node A. A decoupling cap (Cᴇ) placed close to the cell supplies that charge locally, holding the supply steady.
Where ΔI is the current step during switching, Δt is the response time before the PDN/regulator can react, and ΔVallowed is the maximum tolerable voltage ripple. Designers budget decap so the PDN's impedance stays below Ztarget across the relevant frequency range.
Decoupling capacitors supply local charge during a switching current spike, keeping the voltage dip shallow (teal) compared to an undecoupled supply (red) that can sag below the functional minimum.
Decoupling capacitors are placed throughout the design to keep transistors supplied with stable voltage despite switching noise and long-distance power routing. They act as local charge reservoirs that:
Smooth voltage spikes
Absorb sudden current demand from nearby switching logic before it propagates as noise.
Reduce IR drop & Ldi/dt
Supply localized charge during peak switching activity, reducing both resistive drop and inductive transients.
Electromigration (EM)
Electromigration is the gradual displacement of metal atoms in interconnect caused by sustained high current density: the "electron wind" physically pushes metal ions along the wire over time, eventually opening a void on one end and piling up a hillock on the other. Left unchecked this leads to opens, shorts, or increased resistance — a slow, cumulative failure mode rather than an instant one, which is why it is budgeted for the chip's expected lifetime (often 10 years) rather than caught by a single functional test.
J is current density, Ea is the activation energy of the metal (material-dependent), T is temperature, and A, n are process-derived constants. Higher current density and higher temperature both shorten expected wire lifetime — which is why EM limits tighten sharply near hot spots, and why modern signoff increasingly folds in self-heating rather than assuming a flat ambient temperature.
Power and signal EM analysis are required for foundry signoff at every advanced node, and increasingly include self-heating effects and statistical EM budgeting rather than fixed worst-case margins.
Analysis & Signoff
| Check | Purpose |
|---|---|
| Static IR Drop | Verifies average voltage drop across the PDN under nominal current draw |
| Dynamic IR Drop | Verifies voltage drop under realistic, time-varying switching scenarios (vectored or vectorless) |
| Electromigration (EM) | Verifies current density in power/signal wires stays within foundry-qualified limits |
| Decap Budgeting | Ensures sufficient decoupling capacitance is placed to meet dynamic voltage targets |
| Chip-Package-System (CPS) Co-analysis | Extends PI analysis across die, package, and board together |
Subtopics
EMIR Analysis Ready
Static & dynamic analysis, Power/Signal EM, package co-analysis, Sigma-AV/DVD, ROM, and multi-die signoff, in depth.
UPF Coming soon
Unified Power Format — describing power intent, domains, and low-power design constraints.
Sources
- IR Drop in VLSI: A Beginner's Guide — GTR Academy
- Understanding Power Integrity as a System-Wide Challenge — Electronic Design
- Voltus IC Power Integrity Solution — Cadence
- Decap Cells in VLSI Physical Design — Medium
- Power Integrity in Physical Design: Key Strategies & Solutions — Takshila VLSI
- IR-Drop in On-Chip Power Distribution Networks of ICs With Nonuniform Power Consumption — IEEE Xplore
- Black's Equation for Today's ULSI Interconnect Electromigration Reliability — A Revisit — IEEE Xplore
- Electromigration Check: Where the Design and Reliability Methodologies Meet — IEEE Xplore