<?xml version="1.0" encoding="UTF-8"?>
<urlset xmlns="http://www.sitemaps.org/schemas/sitemap/0.9">
  <url>
    <loc>https://vlsi-atlas.com/</loc>
    <lastmod>2026-08-11</lastmod>
  </url>
  <url>
    <loc>https://vlsi-atlas.com/Logic_Synthesis.html</loc>
    <lastmod>2026-08-11</lastmod>
  </url>
  <url>
    <loc>https://vlsi-atlas.com/Standard_Cell_Library.html</loc>
    <lastmod>2026-08-11</lastmod>
  </url>
  <url>
    <loc>https://vlsi-atlas.com/Advanced_Synthesis_Techniques.html</loc>
    <lastmod>2026-08-11</lastmod>
  </url>
  <url>
    <loc>https://vlsi-atlas.com/Physical_Design.html</loc>
    <lastmod>2026-08-11</lastmod>
  </url>
  <url>
    <loc>https://vlsi-atlas.com/Static_Timing_Analysis.html</loc>
    <lastmod>2026-08-11</lastmod>
  </url>
  <url>
    <loc>https://vlsi-atlas.com/Tapeout.html</loc>
    <lastmod>2026-08-11</lastmod>
  </url>
  <url>
    <loc>https://vlsi-atlas.com/Fabrication.html</loc>
    <lastmod>2026-08-11</lastmod>
  </url>
  <url>
    <loc>https://vlsi-atlas.com/Power_Integrity.html</loc>
    <lastmod>2026-08-11</lastmod>
  </url>
  <url>
    <loc>https://vlsi-atlas.com/EMIR_Analysis.html</loc>
    <lastmod>2026-08-11</lastmod>
  </url>
  <url>
    <loc>https://vlsi-atlas.com/UPF_IPF.html</loc>
    <lastmod>2026-08-11</lastmod>
  </url>
  <url>
    <loc>https://vlsi-atlas.com/Low_Power_Design.html</loc>
    <lastmod>2026-08-11</lastmod>
  </url>
  <url>
    <loc>https://vlsi-atlas.com/DFT.html</loc>
    <lastmod>2026-08-11</lastmod>
  </url>
</urlset>
