EMIR Analysis

Static Analysis

Static IR-drop and static EM analysis evaluate the power delivery network (PDN) under average, steady-state current rather than instant-by-instant switching. It's the fast, always-available baseline check, run early and continuously through physical implementation, because it doesn't need switching vectors and it catches the majority of structural PDN weaknesses — thin straps, missing vias, undersized rings — before dynamic data even exists. In a general signoff flow, static and dynamic analysis are complementary and both mandatory: static is the cheap, constant baseline; dynamic is the expensive, higher-fidelity check layered on top.

How it works

The general method computes voltage drop as a simple linear system: an average current per instance is derived from toggle rate and power data, the PDN is extracted into a purely resistive network (capacitance and inductance are irrelevant for a DC, non-transient solve), and V = I·R is solved at every node — typically with a sparse conjugate-gradient-style solver. This is a deliberate simplification: no timing correlation between switching events, no transient current shape, no package/inductive effects. It's pessimistic in some ways (assumes currents overlap) and optimistic in others (it can miss a brief, localized simultaneous-switching spike that only dynamic analysis would catch).

Solved as a DC linear network (no C, no L) across the full extracted PG mesh — the same Ohm's-law relationship covered on the Power Integrity page, applied here specifically to average/steady-state current rather than a single switching event.

Inputs

Activity-source flows

Outputs

Instance-level and summary power reports broken down by power domain, frequency domain, and user-defined groups (combinational / sequential / memory / decap) — reporting internal, leakage, switching, and total power, toggle rate, and voltage per instance/pin. These feed directly into the static DC voltage-drop solve and static EM current-density checks. Coverage statistics (VCD annotation coverage, % of instances with power data) are reported alongside and are an important sanity check before trusting the results.

Best practices & pitfalls

X-states in VCD must be explicitly resolved (treat as 0, as 1, as toggle, or ignore — "ignore" is the default but isn't always right for dynamic feed-through). IPF coverage should be verified as near-100%, or a hybrid activity-driven flow is recommended instead. Precedence rules matter and are easy to get wrong: settings precedence runs leaf-instance > cell > block > design-wide values > tool defaults, and activity-source precedence runs propagation < default activity < constant/X-driven signals < STA/library-derived constants < explicit SAIF/VCD data.

Power Grid Robustness Checks

Before — or even instead of — a full static or dynamic voltage-drop run, a set of purely structural checks can verify the PDN is built correctly in the first place: no shorts, no disconnects, no missing vias, and no locally weak regions that could cause problems no matter what current is later applied. This is what "power grid robustness" refers to across EMIR signoff: several of these checks need nothing but LEF/DEF geometry — no timing, no switching activity, no vectors — so they can run extremely early, as soon as basic power grid construction is complete, well before the design has clean STA or activity data for the stages above.

The six robustness checks

SPR and Reff are dominated by whichever layer contributes the most resistance — usually Metal1 — so a weakness introduced above that layer, or a weakness that only shows up once current is actually distributed realistically across a rail, can slip through both checks looking completely healthy.

Why BQM catches what SPR and Reff miss

SPR reports the single shortest resistive path from a point to a voltage source, and Reff reports the parallel combination of every path to every bump — but neither actually distributes current the way a real grid would; each is effectively an isolated, idealized measurement. BQM instead places many small current probes evenly along a chosen metal layer (probe spacing and total current, or current-per-micron, are both configurable) and runs an actual lightweight simulation, so the resulting voltage heatmap reflects genuine current distribution through the grid as built. The documentation's own example is concrete: a long Metal1 rail feeding a memory channel with no upper-layer via connection showed over 200mV of drop under BQM, while SPR and Reff both reported that same rail as fine, because most of their computed resistance was already concentrated in Metal1 and neither method actually pushed current through the rail the way BQM does.

Because BQM only needs LEF/DEF and a chosen check layer — no timing, no activity, no vectors — it can run as soon as the basic power grid exists, long before static or dynamic analysis (Stages 1 and 2 above) have the data they need. A related technique, peakTW, statistically combines BQM's structural current probes with local simultaneous-switching timing-window data, catching grid weaknesses that only emerge under combined structural-and-switching stress — directly addressing the scale problem full dynamic simulation runs into on very large designs (the documentation cites designs with 10B+ extracted geometries and 2B+ instances as the scale where exhaustive dynamic coverage becomes impractical).

Where this fits in the flow

These checks aren't a replacement for static or dynamic analysis — they're a cheap, early, structural complement to them. Shorts and disconnect checks run by default as part of extraction. SPR, Reff, BQM, and missing-via checks are opt-in but inexpensive relative to a full analysis run, and are exactly what powers the lightweight "chip-only PDN quality check" mentioned under Multi-Die / Multi-Chip Analysis for sanity-checking bump and grid density before committing to a full multi-die EMIR run.

Dynamic Analysis

Dynamic voltage-drop (DVD) analysis models the instantaneous, time-varying response of the PDN to real or synthesized switching events — capturing localized simultaneous-switching noise and di/dt-driven drop that static (average-current) analysis simply cannot see, because it requires full transient (RLC) simulation of the PG mesh driven by time-stamped current sources at every instance's power pins.

Sub-techniques & variants

Key metrics reported

EM signoff run on the same dynamic scenario produces RMS and Peak EM reports for metal and vias, and a Switching Coverage Report (per cell-type, per frame) tracks how much of the design actually toggled during a vectorless run — an important confidence metric alongside the voltage numbers.

Best practices & pitfalls

Long scenario durations and large partitioned blocks strain Logic Propagation runtime and memory, which is why NPV is favored full-chip and PCVS/Logic Propagation at block level. Target power for PCVS has to be realistic — too close to the all-off (leakage) floor or the all-on ceiling makes it unachievable without distorting activity. Macro default behavior (switching only per input-pin logic state) is a common source of power-estimate variance between scenarios unless explicit mode control is applied. For VCD-based NPV, start-time misalignment between the VCD and clock-period edges is a known limitation that can corrupt timing-window voltage statistics unless corrected. Saving full instance-level voltage/current waveforms is computationally and disk expensive and should be reserved for debug, not full signoff runs.

Power EM

Power EM checks the current-carrying wires and vias of the power delivery network itself — the VDD/VSS routing — for electromigration risk. Electromigration is the physical transport of metal ions caused by momentum transfer from flowing electrons to the metal lattice; over time this produces voids (opens, from ion depletion at the cathode end) or hillocks (shorts to neighboring wires, from ion pileup at the anode end). Power nets are the highest-risk EM candidates in practice because current flows in a predominantly unidirectional, DC-like direction from supply pads down to the standard cells — there's no reverse-current "self-healing" the way there is on a switching signal net.

How it works

Power EM is not a standalone simulation — it consumes the currents already computed by static or dynamic voltage-drop analysis. In static analysis, EM checking uses true average (DC) current density for wires and current-per-cut (or per-area) for vias. In dynamic analysis, three current metrics can be checked: average/DC, RMS, or peak. DC/average current is compared against foundry limits derived from Black's equation, which foundries use to back-calculate a maximum allowable current density for a target lifetime. RMS current checks guard against Joule (self-)heating — I²R heating raises local wire temperature, which accelerates the ion-diffusion process behind EM — and this check can be back-annotated with real thermal-solve temperatures rather than a flat assumed ambient. Peak current checks guard against localized melting from momentary current spikes; foundries generally don't cleanly define duty-cycle-based peak limits for power/ground nets, so tools typically fall back conservatively to the smallest peak limit defined for a given layer.

Inputs

Outputs

EM heatmaps for metal/via current and violation percentage; a violation browser listing the worst offenders (typically capped at a large number, e.g. the top 1000) with a "sliver" flag column; text reports per metal segment and via (layer, coordinates, length, width, current, EM constraint, violation %, status, net, current direction); and an optional Failure-in-Time (FIT) calculation reporting an aging/failure-rate metric against a target lifetime (a common default is 5 years).

Best practices & pitfalls

Sliver handling is a recurring special case: artificial, sub-minimum-width shapes created during LEF/DEF geometry merge/fracture operations aren't real wires but appear in extraction/EM flows. They can be filtered out, but shouldn't be blanket-suppressed — offset-connected slivers can represent genuine violations, so they should be spot-verified rather than ignored wholesale.

Signal EM

Signal EM checks electromigration risk on logic and clock interconnect rather than power/ground rails. The key difference from Power EM is the current waveform: signal-net current is dynamic and often bidirectional — a driver charges the net on one edge and discharges it on the other — whereas power-rail current is essentially unidirectional. Because reverse-direction current partially "heals" prior ion displacement, RMS/AC EM limits for signal nets are typically higher than DC limits for an equivalent power net — though clock nets remain a significant risk on their own, thanks to very high switching activity and minimum-pitch routing.

How it works

Rather than reusing IR-drop currents, signal EM current is built from driver-current and receiver-capacitance models in the timing library (RedHawk-SC uses CCS-Timing / CCST data, described as the most accurate available method for this purpose). Bidirectional average current is handled via the recovery-factor formula above — r = 0 means no recovery credit (worst of charge/discharge is used), r = 1 means full recovery credit, r = −1 sums charge and discharge (most conservative, and the documented default). RMS checks use a self-heat temperature tolerance plus a foundry-supplied relaxation factor, analogous to Power EM. Peak checks are duty-cycle aware — the minimum duty ratio and maximum pulse width are computed directly from the actual switching waveform, unlike power/ground nets where duty cycle is poorly defined.

Inputs

Outputs

The same heatmap/violation-browser mechanism as Power EM, plus signal-specific reports: a Dropped Nets Report listing nets excluded from analysis entirely (constant nets, multi-driver conflicts, missing driver/receiver, disconnected receivers, missing capacitor data, driver-receiver shorts), a Dirty Nets Report listing nets analyzed using tool-default values because of incomplete data (missing frequency, slew, driver voltage, SPEF capacitance, or inconsistent multi-driver frequency/waveform data), and a Signal Net Info Report capturing per-net voltage, frequency, toggle rate, slew, capacitance, and domain.

Special case: clock mesh / multi-driver nets

Clock meshes — shorted grids driven by many buffers to reduce skew — are a distinctive challenge for signal EM. The default assumption evenly splits load across mesh drivers and, absent arrival-time data, fires all drivers simultaneously — acceptable for early analysis but not signoff-accurate. For signoff, driver currents can instead be supplied from SPICE-derived waveform files, with every driver on a given multi-driven net needing full waveform coverage or the net falls back to the default (less accurate) method.

Best practices & pitfalls

Missing CCS-Timing data degrades accuracy and should be checked for in the run log before trusting results, as should dropped/dirty net counts. A recheck mechanism can automatically re-examine near-violating segments with finer geometric analysis to reduce false positives (a common threshold cited is around 85% of the limit). The general debug sequence: confirm the net isn't dirty or dropped, verify activity/frequency/SDC inputs, then check the recovery factor and thermal/lifetime factors for average violations, self-heat parameters for RMS, and duty-ratio/pulse-width data for peak violations.

Dynamic Analysis with Package Analysis

Chip-level dynamic analysis conventionally terminates the PDN at the C4 bumps or BGA balls with an idealized voltage source — but the die doesn't actually see an ideal voltage; it sees whatever the package and board deliver, filtered through their own parasitic impedance. The package (bond wires, BGA balls, redistribution layers, vias) and the board (planes, traces, VRM output impedance) each contribute resistance, inductance, and capacitance that, combined with on-die decoupling capacitance, form a multi-stage RLC ladder. This composite network exhibits impedance peaks — anti-resonances — and if a chip's switching activity has spectral content near one of those resonant frequencies, the resulting voltage droop can be far worse than a die-only simulation would ever predict, because the source impedance seen by the die is amplified rather than damped at that frequency. This is why the industry frames it as a chip-package-system (CPS) problem: on-die decap, package decap, and board/bulk decap each cover a different frequency band, and only a combined analysis can verify that coverage is continuous with no resonance gap.

L is the aggregate loop inductance up to a given decoupling stage (on-die, package, or board), C is the capacitance available at that stage. Switching activity with spectral energy near f_res excites an impedance peak in the PDN, producing worse droop than a flat-impedance assumption would suggest.

How it works

Rather than fully co-simulating a single merged electromagnetic mesh across die, package, and board, the common approach appends an off-chip network model to the on-die extracted PDN netlist at simulation time, at one of three increasing levels of fidelity:

The die-side connection is established through a bump/pad location mapping file linking physical bump names to package SPICE ports. Voltage levels are always taken from the on-die scenario definition, not from the package netlist, so package-side source voltages are normalized relative to that ideal voltage. Pre-simulation time is typically auto-determined so the transient doesn't start before parasitic ringing from applying the package model has settled.

Special cases

HBM stacks and multi-die packages: a full 3D-stacked HBM has millions of interconnect bumps, so per-bump connection is impractical. Instead, each HBM chiplet is reduced to a Chip Power Model (CPM) — a compact SPICE model of the die's PDN plus its currents, with ports grouped down to a tractable count. In a model-based flow, HBM dies are represented purely by their CPMs while the logic die and interposer retain full detailed-layout IR simulation, producing combined IR-drop and EM results across the whole stack.

Wide-bus simultaneous switching (SSO): a dedicated utility parses an RTL-to-gate bit-mapping file (from formal-verification tools) to auto-detect wide parallel buses — DDR/HBM-width data buses — determine each bus's clock domain, and synthesize a worst-case stimulus with every bit toggling together at a user-specified probability and clock period. This directly targets SSO noise: many I/O drivers switching simultaneously create large instantaneous di/dt through shared package/board inductance, producing ground bounce or power-rail droop severe enough to cause timing failures on DDR-class interfaces.

Best practices & pitfalls

Port-count management matters a lot: a few hundred to a few thousand package ports is the recommended range — beyond roughly ten thousand ports, accuracy improvement in dynamic voltage-drop results becomes negligible while runtime suffers, so port grouping during package extraction is recommended. S-parameter models specifically should generally stay under about 100 ports (a practical sweet spot around 50–60). A mismatched or missing package subcircuit name can silently exclude the package model from simulation rather than failing the run outright, so this is worth double-checking.

Sigma-AV / Sigma-DVD Analysis

Sigma-DVD is a statistical/combinatorial alternative to transient vector-based dynamic IR-drop simulation, aimed squarely at a failure mode that plagues traditional transient analysis: local switching-noise coverage. Transient simulation — vectorless or vector-based — can only exercise a finite, small number of clock cycles, while the number of distinct simultaneous-switching combinations among a victim cell's neighboring "aggressor" cells is combinatorial. Reaching full coverage this way would require an impractical number of clock cycles — practically impossible for any real design. Transient results are also acutely sensitive to timing-alignment noise and simulation time-step size, both of which can shift reported drop by tens of percent between otherwise-similar runs.

Even a modest 9 aggressor cells around one victim yields 512 distinct switching combinations — and a real victim cell can have far more than 9 neighbors. Exhaustively simulating this combinatorial space with transient vectors is infeasible; statistical sampling is the practical alternative.

What each name means

How it works

The foundational unit is voltage impact: the drop a specific aggressor instance induces on a specific victim, computed via extensive pairwise simulation — essentially a superposition/impedance characterization, conceptually similar to library characterization. The aggressor universe per victim is then filtered by timing windows (does the aggressor's legal switching window overlap the victim's?) and logic/correlation constraints (cells that must switch together — e.g. buffer chains, correlated bus bits — are grouped so physically-impossible combinations are excluded), and the remaining combinations are sampled statistically rather than exhaustively enumerated, with a configurable joint-probability cutoff controlling how aggressively combinations are admitted. The reported drop is typically the average voltage drop over the victim's own switching window — the period during which its output is transitioning — because this correlates better with actual gate-delay pushout than a raw peak or minimum voltage metric. Local switching noise like this is estimated to make up roughly 80% of a typical instance's total voltage drop, which is why coverage of exactly this piece matters so much.

This mirrors a broader shift already well established in static timing analysis: flat worst-case corner methodology (assuming rare conditions occur simultaneously everywhere) has long been recognized as overly pessimistic, and the industry's general answer has been statistical/parametric on-chip variation — modeling each quantity as a probability distribution and signing off at a defined sigma point (commonly 3σ) rather than an absolute worst case. Sigma technology for power integrity follows the same philosophy applied to voltage drop instead of timing.

Inputs & outputs

Best practices & pitfalls

Non-functional scan/test clocks should be filtered out of timing windows before running, or they generate large numbers of bogus aggressors. PDN grid quality should be verified before trusting aggressor-driven failures — a grid that can't even support a victim's own self-switching current will swamp results with unrelated failures. It's normal, not a defect, for a well-run sigma analysis to report more failures than an equivalent transient run — that's the point of having exhaustive coverage instead of a handful of sampled scenarios.

ROM Analysis

In this context "ROM" means Reduced Order Model, not read-only memory. Full-chip EMIR signoff on modern SoCs is bottlenecked by raw scale: hundreds of power domains and billions of devices/nodes/resistors are common, and full-chip runs can require thousands of CPU cores, terabytes of memory, and one to three days to complete — with a costly re-run if anything fails. Traditional divide-and-conquer partitioning (splitting the chip into arbitrary regions) doesn't solve this cleanly either: it causes systematic inaccuracies, false violations at partition boundaries, and painful results-consolidation, and typically only supports static checks or a handful of transient cycles rather than full coverage.

ROM exploits a structural fact about large SoCs instead: the same block (macro/IP) is often instantiated many times. Rather than re-simulating every instance's full internal PDN detail at the top level, ROM generates one compact abstract model per unique block and reuses it across every instance of that block — cutting compute drastically while aiming to preserve signoff-level accuracy at the block boundary.

How it works

The flow is bottom-up and two-stage. First, ROM generation runs at the block level, taking the block's simulation, scenario, and analysis data and producing a compact abstraction of its electrical behavior at its boundary. Second, at the full-chip level, the generated block ROM(s) are loaded and each instance in the design is marked either "reduced" (uses the ROM) or "detailed" (full standard-cell/layout-level model) — mixed use is explicit and encouraged, e.g. keeping a handful of high-risk instances detailed while reducing the rest.

The core abstraction mechanism is layer-based rollup at the block boundary: a "connection layer" is specified as the metal layer where the block physically interfaces the top-level grid, detail is preserved down to two layers below that connection layer, and everything below is lumped into an equivalent compact representation — conceptually comparable to industry-standard RLC macromodeling techniques (Krylov-subspace moment-matching methods are the general academic reference point), though the internal reduction algorithm itself isn't publicly disclosed. Picking a connection layer that doesn't match where the block actually interfaces the top grid produces inaccurate rollup results.

Multiple workload scenarios (current profiles) can be characterized and stored in a single block ROM, then selected per-instance at the top level — chained in time order, mixed statistically, or time-shifted — so many instances of the same block can realistically simulate different switching behavior without re-simulating the block itself. Two controls trade accuracy against cost: a detail level (low/medium/high) tuning fidelity of the abstraction, and a compression setting trading disk footprint against runtime for the stored model files. The same reduction extends to signal EM: instead of re-analyzing a block's internal signal nets (already signed off at block level), the block-level run archives just its boundary net data, and the full-chip run only analyzes top-level nets plus those interface nets.

Validation before trusting a ROM in signoff

Sanity checks compare the ROM's decap statistics and total demand currents against the original block-level analysis (essentially a diff between ROM data and the ground-truth analysis view) and report any physically or logically disconnected pins. Current and decap detail, and the settings baked into a given ROM (connection layer, rollup layer, skipped layers, accuracy level), can all be inspected before it's trusted for full-chip signoff.

Flat vs. ROM: a real comparison

One internal benchmark comparison (a large real design, flagged here as a single customer case study rather than a guaranteed general result) illustrates the scale of savings: structurally, instance count dropped from roughly 68.8M to 40.7M (a 40.8% reduction) and via instances from about 1.1B to 0.53B (51.4% reduction), with the entire design's many hierarchical instances represented by only 3 distinct ROM cells. On resources, total runtime dropped from 13h 44m to 9h 40m (29% reduction), memory footprint from 3.1TB to 1.8TB (42% reduction), and database size from 604GB to 353GB (41% reduction) — with the largest stage-level speedup in the analysis-view stage itself (3h 12m → 55m, a 71% reduction). Accuracy correlation between the flat and ROM runs showed only a small number of instances deviating more than about 0.2% (roughly 2mV) from the flat-run voltage, and every instance stayed within about 1.2% — a level of agreement the case study treats as acceptable for signoff use.

Relationship to Chip Power Model (CPM)

CPM is related to ROM but serves a different purpose. It isn't the ROM flow itself, though it's built on the same underlying reduced-order-modeling engine internally. CPM's job is external: it produces a compact, portable SPICE netlist representing the entire chip's PDN as an equivalent circuit at its bumps or pads, for package and board designers doing die-package-board co-design outside the EMIR tool entirely (impedance/resonance checks, decap placement, voltage-margin validation in a general SPICE simulator — feeding directly into the package-analysis methodology from Stage 5). ROM, by contrast, is consumed inside the EMIR tool to make full-chip signoff itself scalable by reusing block-level results. A distributed variant of CPM removes the single-worker, memory-heavy bottleneck of the classic approach by building the model hierarchically across distributed workers instead — the same scalability principle ROM applies to full-chip EMIR, applied to chip-level package modeling instead.

Best practices & pitfalls

Connection-layer choice is the single highest-leverage accuracy control and must match the block's real physical interface to the parent grid. A ROM is a frozen snapshot of the scenario(s) it was generated with — if the block's PDN, decap, or physical implementation changes, or a new workload needs to be checked, the ROM has to be regenerated, not assumed still valid. Mixed reduced/detailed usage is the recommended middle ground for instances judged especially critical.

Multi-Die / Multi-Chip Analysis

Single-die EMIR signoff assumes one PDN bounded by a single die's package interface. In 2.5D/3D packaging — chiplets mounted side-by-side on an interposer, or dies stacked vertically and joined by through-silicon vias (TSVs) or hybrid bonding — multiple dies share a single physical PDN spanning die → micro-bump/TSV → interposer → package → board. Current drawn by one die's switching activity propagates through shared TSVs, bumps, and interposer metal, causing IR drop and EM stress in a neighboring die's power network — a cross-die coupling effect single-die analysis cannot capture on its own, since neither die's PDN is electrically independent of the other's.

Bonding technology trends make this steadily more important: the industry has moved from C4 solder bumps (roughly 125µm pitch) to copper-pillar micro-bumps (roughly 40µm pitch) to hybrid bonding (roughly 6µm pitch, direct copper-to-copper with no bump at all) — each step shrinking the physical connection while concentrating current density and raising local EM risk at the die-to-die interface itself, on top of the usual on-die and package EM concerns.

How it works

Each die keeps its own per-die model (design, extraction, timing, scenario, and simulation data), unified through additional views layered on top: a configuration view describing die sizes, instance names, interface/connection-point locations, per-connection-point parasitics, and the package interface; a coupling view extracting the electromagnetic coupling parasitics between neighboring dies (not just simple point-to-point connections); and a unified multi-chip analysis view running the combined simulation, from which individual per-die results are retrieved using the same APIs as single-die analysis. The same underlying simulation engine is used for single-die and multi-die analysis — the difference is that scenario and simulation data from all dies is connected and combined before solving, rather than solved independently.

Analysis methods

TSV modeling

TSVs are modeled either directly from foundry technology-file data (when the foundry provides TSV RC/RLC parameters), or via a user-supplied SPICE subcircuit with reserved "top" and "bottom" nodes mapping to the metal layers above and below the via — commonly a simple π-model of two series resistors flanking a shunt capacitance to ground.

Inputs

Outputs

Cross-die IR drop per instance, computed with the shared-PDN coupling effect included, plus system-level aggregation across bump currents and voltages; TSV/bump EM (with both DC and dynamic/transient modes); inter-die signal EM for signal nets crossing die boundaries through connection points; and a multi-chip shortest-path-resistance check that traces the resistive path from any instance pin, across die and interposer boundaries, all the way to the package bumps — producing both heatmaps and an explicit per-segment path table, directly useful for diagnosing why a particular instance sees excess IR drop.

Best practices & pitfalls

There's typically no native "multi-chip-level" report — results are retrieved per individual die using the same reporting APIs as single-die analysis (the shortest-path-resistance check is the one exception with its own dedicated multi-chip report). Dummy scenario data is needed for dies with no active cell instances (e.g. a passive interposer) to keep scenario type/duration consistent across every die in the joint analysis. The external-Chip-Power-Model approach works best for topologies where all dies connect to one interposer hub, and gets noticeably harder for interposer-less structures like wafer-on-wafer or die-on-integrated-circuit stacking, where dies aren't all tied to one common reference die. Connection-point names must be globally unique across the whole multi-die configuration.

Glossary

Sources

This page draws on internal Synopsys RedHawk-SC application notes and training material (Static/Dynamic Power Analysis, Early Grid Analysis & Robustness Checks, BQM & PeakTW, Power & Signal Electromigration, Die/Package/Board Analysis, HBM Modeling, Sigma-AV/Sigma-DVD/Sigma-PD, ROM, Chip Power Model, and Multi-Chip/3DIC Analysis app notes and training decks), supplemented with general web research on each topic's industry-standard methodology, cited below.

• IR-Drop in On-Chip Power Distribution Networks of ICs With Nonuniform Power Consumption — IEEE Xplore
• IRDrop Analysis in Power Delivery Network Design — IEEE Xplore
• Fast Vectorless Power Grid Verification Using Maximum Voltage Drop Location Estimation — IEEE Xplore
• Full-Chip Vectorless Dynamic Power Integrity Analysis and Verification — IEEE Xplore
• Dynamic Voltage (IR) Drop Analysis and Design Closure: Issues and Challenges — IEEE Xplore
• Power grid robustness / structural PDN checks (shorts, disconnects, SPR, Reff, BQM, missing via) — AppNote_Early_Grid_Analysis_and_Robustness_Checks.pdf, AppNote_Early_Grid_Analysis_using_BQM_and_peakTW.pdf (internal Synopsys/Ansys RedHawk-SC documentation)
• Black's Equation for Today's ULSI Interconnect Electromigration Reliability — A Revisit — IEEE Xplore
• Electromigration Check: Where the Design and Reliability Methodologies Meet — IEEE Xplore
• Modeling Electromigration Lifetime Under Bidirectional Current Stress — IEEE Xplore
• Full-Chip Signal Interconnect Analysis for Electromigration Reliability — IEEE Xplore
• Chip-Package Power Delivery Network Resonance Analysis and Co-Design — IEEE Xplore
• System Level Power Integrity Analysis with Physics-Based Modeling Methodology — IEEE Xplore
• Extended CPM for System Power Integrity Analysis — IEEE Xplore
• Analysis of Dynamic Voltage Drop with PVT Variation in FinFET Designs — IEEE Xplore
• Fast Statistical Analysis of Rare Circuit Failure Events via Scaled-Sigma Sampling — IEEE Xplore
• Reduced-order/macromodel benchmark comparison (flat vs. ROM runtime/accuracy) — Flat_and_ROM_Comparison.pdf (internal Synopsys/Ansys RedHawk-SC documentation)
• Model and Analysis for Combined Package and On-Chip Power Grid Simulation — IEEE Xplore
• Fast Dynamic Simulation of VLSI Circuits Using Reduced-Order Compact Macromodel of Standard Cells — IEEE Xplore
• Electromigration Study for Multi-Scale Power/Ground Vias in TSV-Based 3D ICs — IEEE Xplore
• System-Level Comparison of Power Delivery Design for 2D and 3D ICs — IEEE Xplore