Physical Design

Floorplanning

Floorplanning decides the chip's physical skeleton before a single standard cell is placed: the size and aspect ratio of the core, where hard macros and IP blocks sit, where power straps run (see Power Integrity), and which physical-only cells need to be pre-planned so that placement, CTS, and routing all have a legal, manufacturable starting point.

Core sizing, utilization, and macro placement

The core area is sized from a target utilization — core size ≈ (standard-cell area + macro area + blockage area) / utilization — with typical targets around 70–80%. Push utilization too high and routing congestion, timing degradation, and DRC violations follow; too low wastes die area and adds wire length. Hard macros (SRAMs, analog IP) are placed first since standard-cell placement is planned around them, driven by connectivity/adjacency to I/O and other macros, orientation (flipping/rotating to align pins), and leaving clear channels for standard-cell rows and routing. A macro halo is a keep-out margin around a fixed macro where no other macro or standard cell may be placed, guaranteeing routing/DRC clearance; it moves with the macro if relocated. Placement/routing blockages (hard, soft, partial, or layer-specific routing blockages) reserve regions for later use — for example, protecting space for a clock mesh or a power strap before anything is placed there.

Design-rule compliance ahead of placement (“TCIC”-style checks)

Some flows run a class of pre-placement expert/compliance checks at advanced nodes before global placement begins — verifying, for example, that a floorplan's planned tap-cell grid actually satisfies the foundry's max-distance-to-tap rule before real cells exist to test it against. If your flow documentation refers to this by a specific internal acronym, treat it as this general category of check: a DRC-style sanity pass on the floorplan's physical-only cell grid (tap/boundary spacing) run ahead of placement, not a check on functional logic. The one rule underneath it that is universal and rock-solid is the tap-cell distance rule described below.

Boundary (end-cap) cells

Ordinary standard cells are drawn assuming abutment with a neighbor on both sides — their well, diffusion, and poly layers are meant to continue into whatever sits next to them. A cell placed at the literal edge of a row or block would expose an unterminated well/diffusion boundary, producing well-spacing violations, dangling active diffusion, and poly-density/lithography loading problems. Boundary (end-cap) cells are physical-only cells with no logic function, placed at both ends of every standard-cell row and at block/macro boundaries, that provide proper well/diffusion termination and dummy poly for uniform lithography loading. They are fixed (never moved by the placer) and connect only to power/ground.

Tap cells and the max-distance-to-tap rule

Bulk CMOS has an inherent parasitic PNPN thyristor structure formed by adjacent NMOS/PMOS devices. If triggered by noise or a transient, this structure can latch into a low-impedance short from VDD to GND — latch-up. Tap cells tie the N-well to VDD and the P-substrate/P-well to VSS at regular intervals, and the latch-up holding current depends strongly on the well/substrate resistance between a transistor and its nearest tap: the farther a transistor sits from a tap, the higher that resistance, and the smaller the trigger current needed to sustain the parasitic thyristor. The foundry Design Rule Manual specifies a maximum allowed distance from any transistor to its nearest tap (commonly on the order of 15–30 µm, tighter at advanced nodes) precisely to bound this resistance. Because most standard cells contain no built-in tap, tap cells are inserted as a separate, regular staggered/checkerboard grid across the whole core during floorplanning — before placement — so that wherever real cells later land, every point on the die is guaranteed to be within the rule.

Spare cells for ECO

A bug found late — in signoff, or worse, in post-silicon bring-up — is extremely expensive to fix by full re-synthesis and re-place-and-route, and it risks a new mask set for the lower (diffusion/poly/contact) layers. Spare-cell banks are unconnected (tied-off) logic gates — typically a mix of NAND, NOR, inverters, buffers, AOI/OAI complex gates, muxes, and flip-flops at varying drive strengths — pre-placed and distributed throughout the floorplan during this stage. When a late fix is needed, an ECO tool identifies nearby spare gates and rewires only the upper metal layers to patch in the new logic function, avoiding any change to the expensive lower mask layers. More advanced flows use metal-configurable gate-array spare cells (undefined transistor-level primitives that are turned into a NAND, NOR, XOR, etc. purely by their metal/via connections at ECO time), which pack more logic flexibility per unit area and avoid the idle leakage of pre-defined, unused spare gates. Spare banks are distributed rather than centralized specifically so that wherever a fix is needed later, spare gates are physically nearby, minimizing the ECO's routing detour and disturbance to already-closed timing.

Placement

Placement assigns a legal (x, y) position to every standard cell within the floorplan established above. It runs in three phases — global placement, detailed placement, and legalization — and it's also where the flow's first explicit statement of clock timing risk, the SDC clock uncertainty margin, becomes load-bearing.

Because raw wirelength minimization doesn't guarantee routability or timing closure, placers layer two things on top of the base objective: congestion estimation (predicted routing demand vs. track supply per region, informing white-space allocation) and timing-driven optimization, most commonly via net weighting — giving critical-path nets more weight in the wirelength objective, since a full STA-in-the-loop placement is accurate but expensive. Later, small incremental (ECO) placements add, remove, resize, or nudge a handful of cells to fix a specific violation without disturbing already-closed timing and congestion elsewhere.

SDC clock uncertainty at the placement stage

set_clock_uncertainty applies a timing margin to setup and/or hold checks for a clock, and it bundles three physically distinct effects into one number: clock jitter (period-to-period or cycle-to-cycle deviation from the PLL/clock source), clock skew (spatial variation in arrival time across sequential elements), and a general margin for effects not otherwise modeled. Setup and hold get different values — setup uncertainty is subtracted from the data-required time (tightening the launch-to-capture window), hold uncertainty is added (widening the hold window) — a common industry rule of thumb starts around 10% of the clock period for setup and roughly 5% for hold, refined once real data exists.

Clock Tree Synthesis

CTS connects the clock source to every sequential element's clock pin with a calibrated network of buffers/inverters and routing. It optimizes four coupled objectives at once: skew (arrival-time difference between sequential elements — the goal is small and controlled, not zero, since simultaneous switching of every flop would spike IR drop and di/dt noise), insertion delay / latency (root-to-sink delay — enough to be safe for hold, as little as possible to save power), transition/slew (a maximum-transition design rule at every branch so no segment is too sluggish for the library's characterized range), and useful skew (deliberately unbalancing arrival time so a path with slack "lends" time to an adjacent critical path). The clock network is commonly cited as the single largest source of dynamic power on a chip — often 30–50%+ of total dynamic power — since every clock net toggles every cycle whether or not downstream logic does useful work, which motivates almost everything below.

Types of clocks in a design

Clock gating in detail

Clock gating disables toggling into idle logic to cut dynamic power — industry figures commonly cite 20–40% total dynamic power savings from effective gating. A naive implementation ANDs the clock directly with a combinational enable, but that enable can change state at an arbitrary point in the clock's high phase (it has no timing relationship to the clock edge). If it falls while the clock is high, the AND output drops mid-pulse — a runt glitch reaches downstream clock pins, risking spurious capture. The fix is the Integrated Clock Gating (ICG) cell: a negative-level-sensitive latch captures the enable, feeding an AND gate with the clock. The latch is transparent only while the clock is low and holds as soon as the clock rises, so any transition on the raw enable during the clock's high phase is invisible at the latch output — the AND gate's second input is guaranteed stable for the entire high phase. The result is always either a full, clean pulse or a fully suppressed one, never a partial pulse.

ICG cells are typically placed near the root of a functional sub-tree — after some common buffering, but before the fanout to a whole cluster of leaf flops — so toggling one enable switches off an entire downstream sub-tree at once, maximizing power savings per gating decision. Hierarchical designs layer this: a coarse top-level gate can shut down a whole subsystem while finer sub-module gates inside an active subsystem add extra granularity. The enable signal itself must settle before the gating clock's active edge, which is effectively a setup-like timing requirement on the launch path into the gated sub-tree.

Leaf-level clock distribution

CTS first clusters the (often millions of) sequential leaf cells into physically local groups so each cluster can be driven by a shared local buffer over a bounded wire length — clustering is proximity- and timing-aware, informed by placement data, since leaf-cluster capacitance dominates total clock-tree capacitance. Latency and skew are then balanced level-by-level; the classical algorithmic foundation is Deferred-Merge Embedding (DME), which computes zero-skew (or bounded-skew) embeddings of internal merge points that minimize total wirelength under a delay model, and modern commercial CTS is a descendant of this family extended with useful-skew and dynamically-updated RC extraction. Buffers are inserted level-by-level to restore the clock edge and meet the max-transition rule at every branch, sized per-branch based on downstream load. Because a glitch on the clock net threatens every downstream flop, root/trunk clock nets are routed with non-default routing rules (NDR) — wider wires and spacing than default — and often shielded with adjacent VDD/VSS wires to cap coupling capacitance to a quiet, well-modeled net; leaf/sink-level nets are more often left on default rules to conserve routing resources. Within a "skew group" (a set of flops that must be balanced together), the tool deliberately unbalances arrival times to relax setup on a critical path while capping skew growth to avoid creating new hold violations, and for very large fanout nodes it inserts intermediate buffer stages and splits the fanout across balanced sub-branches.

Clock tree topologies

Routing

Routing connects every placed cell and macro with metal interconnect, in stages: global routing partitions the chip into a coarse grid of tiles and assigns each net a rough path and layer sequence ("routing guides") to check overall routability and spot congestion before committing to exact shapes; track assignment then picks the specific track within each region a wire occupies (increasingly important at advanced nodes with dense non-default rules); detailed routing converts guides into exact geometry — precise coordinates, widths, vias, layer transitions — satisfying the full foundry rule set; and via insertion both handles ordinary layer transitions and inserts redundant/double vias purely to reduce contact resistance and improve yield.

What's checked during and after routing

How uncertainty evolves from stage to stage

The general pattern: STA margin exists to cover unknown information, and each successive stage replaces an earlier necessary guess with measured or extracted reality.

This is the same principle behind pessimism-reduction techniques like common-path-pessimism removal (CRPR) and clock-network pessimism removal — early-stage margins are recognized as necessarily conservative, and the flow actively tightens them as better data becomes available, without giving up safety.

Fillers & Decaps

After placement, CTS, and routing are finalized, empty gaps remain in every standard-cell row. Two kinds of non-functional (or not-purely-functional) cells fill them.

Fillers

Filler cells are non-functional standard cells — no timing arcs, no signal pins — shaped to match the library's row height and site grid so they slot into leftover space. They exist for three physical/manufacturing reasons: (1) well/diffusion continuity — a real standard cell's layout assumes its N-well/P-well and diffusion continue into a neighbor; an unfilled gap leaves those layers discontinuous, causing DRC violations and well-proximity effects that can shift threshold voltage in nearby real cells; (2) density-rule compliance for CMP — chemical-mechanical polishing quality is sensitive to local pattern density of poly/diffusion/metal, and foundries impose minimum (and maximum) density windows per layer; empty rows would create low-density regions causing non-planar CMP and yield loss; (3) power-rail continuity — fillers replicate the VDD/VSS rail segments so the rail stays physically and electrically continuous across the row even where no functional cell exists.

Decaps

Decap (decoupling capacitor) cells are a specialized filler subclass that implement an actual capacitor between VDD and VSS inside the same footprint, typically using MOS transistor gate capacitance. When many nearby cells switch simultaneously, the local power grid must supply a current spike; because the grid has finite resistance and inductance, that spike produces a transient voltage droop (V = IR + L·di/dt) — dynamic IR drop — that erodes setup/hold margin exactly at the switching edges STA assumed were at nominal VDD. Decap cells act as local charge reservoirs, storing and instantly releasing charge to damp that droop faster than the power grid alone can respond, so they're placed close to high-switching-activity logic where effectiveness (which falls off with grid impedance/distance) matters most.

Coarse vs. fine-grained decap — a real two-tier strategy

It isn't strictly "insert everything at the end." Large discrete decap macros are deliberately placed during floorplanning, near big IP blocks or regions of known high switching activity, as part of noise-aware floorplanning — planned early because coarse, global droop mitigation benefits from knowing macro/IP placement upfront (published results cite noise-aware floorplanning cutting peak noise by up to ~40% and overall decap area budget by up to ~21% versus doing it all post-placement). A practical two-step flow: pre-place a uniform decap budget (e.g. roughly 6% of area) before standard-cell placement for baseline coverage, then follow with incremental fine-grained decap insertion (roughly another 1–4% of area) driven by real post-route IR-drop/EMIR signoff results identifying specific hot-spots (see Dynamic Analysis). Fine-grained standard-cell decap fillers are then distributed automatically wherever ordinary fillers would otherwise go, giving local droop suppression right next to whatever logic ended up nearby — since exact locations aren't known until placement legalizes.

Why insertion happens last

Deferring the fine-grained population to after placement, CTS, and routing maximizes usable area for real logic during optimization (fillers would otherwise be legalization obstacles the placer has to shuffle around), avoids blocking routing resources during the router's own optimization, and simply waits until the exact size and location of remaining gaps is actually known. Note the tradeoff on the decap side specifically: decap adds leakage power and, if oversized, can interact adversely with the chip's parasitic RLC network (resonance effects) — so decap budgeting is itself an optimization, not "more is always better."

Interface Paths & Virtual Clocks

Interface (I/O) timing paths cross the boundary of the design being analyzed: input paths (port → internal register), output paths (internal register → port), and feedthrough paths (port → port with no register in between). These need special handling because the logic that actually determines the timing relationship — the external device driving an input, or the external device receiving an output — physically lives outside the netlist being analyzed. STA has no visibility into that external logic's internal delays, so the constraint writer must externally characterize the boundary timing and feed it in as set_input_delay / set_output_delay constraints referenced to a clock edge.

Virtual clocks

A virtual clock is defined with the ordinary create_clock command but is not applied to any physical port or pin — it exists purely as an abstract timing reference (period, waveform, name) that the STA tool never sees toggle anywhere in the netlist. Virtual clocks are used specifically when the clock that actually governs an interface's timing relationship isn't physically present in the design under analysis — for example, a source-synchronous device sharing a board oscillator whose trace connects only to that external device, not to any pin of this chip, so get_ports can't legally reference it. A real clock physically toggles a node and propagates through an actual clock tree (everything covered above); a virtual clock shares the same period/waveform arithmetic but drives nothing — it's a reference for -clock arguments only.

The virtual clock is never attached to a design pin — it exists only so the input/output delay constraints have a reference edge to measure from.

How the delay numbers are actually determined

For a synchronous interface sharing reference period T, the input side must satisfy T ≥ T_co(source device) + T_flight(board trace) + T_setup(this chip's capture register), plus skew/jitter margin. The value passed to set_input_delay -max is essentially T_co(max) + T_flight(max) — "how late data can still arrive relative to the virtual clock edge" — and -min uses the corresponding minimum-case sum for hold analysis. Whatever remains of T after subtracting the input delay is what the chip's own input-to-register logic actually has to work with. The output side is the mirror image: T ≥ T_co(this chip's output path) + T_flight + T_setup(destination device), and set_output_delay reserves the board flight time plus the destination device's setup requirement, so the internal register-to-output-port logic knows how much of the period it's allowed to consume. In both directions, the constraints don't add delay inside the chip — they subtract time from the global period budget, translating external board/device timing into an internal slack number the STA engine can use.

Common pitfalls

Sources

• Multi-Voltage and Level-Shifter Assignment Driven Floorplanning — IEEE Xplore (ICCAD)
• Functional ECO Using Metal-Configurable Gate-Array Spare Cells — IEEE Xplore (DAC)
• Timing ECO Optimization Using Metal-Configurable Gate-Array Spare Cells — IEEE Xplore
• Integrated Circuit Having Tap Cells and a Method for Positioning Tap Cells — US Patent 6,560,753
• Routability-Driven Global Placer Target on Removing Global and Local Congestion for VLSI Designs — IEEE Xplore
• An Efficient Uncertainty- and Skew-Aware Methodology for Clock Tree Synthesis and Analysis — IEEE Xplore
• Zero-Skew Clock Routing With Minimum Wirelength (DME) — IEEE Xplore
• UST/DME: A Clock Tree Router for General Skew Constraints — ACM TODAES
• Optimal Useful Clock Skew Scheduling in the Presence of Variations Using Robust ILP Formulations — IEEE Xplore
• Clock Mesh Framework — IEEE Xplore
• Enhancing Double-Patterning Detailed Routing With Lazy Coloring and Within-Path Conflict Avoidance — IEEE Xplore
• Pessimism Reduction in Coupling-Aware Static Timing Analysis Using Timing and Logic Filtering — IEEE Xplore
• UI-Timer: An Ultra-Fast Clock Network Pessimism Removal Algorithm — IEEE Xplore
• Block-Based Static Timing Analysis With Uncertainty — IEEE Xplore
• Static Timing Analysis Using Derived Boundary Timing Constraints for Out-of-Context Hierarchical Entity Analysis — US Patent 9,542,524
• End-cap/boundary cells, well-tap cell placement, filler and decap cell mechanics — general web research (practitioner references: Team VLSI, iVLSI Technologies, physicaldesign4u)
• SDC clock uncertainty, generated/virtual clock semantics, I/O timing budgeting — general web research (vlsi.pro, Synopsys/Xilinx/Intel constraint documentation)