What "Tapeout" Means
The term dates back to when finished designs were physically shipped to the mask shop on magnetic tape — the tape "went out," hence tapeout. The mechanism has changed completely (design data now transfers electronically), but the meaning hasn't: tapeout is the moment the design team declares the layout database final, hands it to the foundry, and loses the ability to make further changes without paying for new photomasks. Because a full mask set at an advanced node can run into the millions of dollars and take weeks to fabricate, tapeout is treated as a one-way door — every signoff check below exists specifically to make sure nothing has to be caught after this point rather than before it.
This is also why the spare-cell ECO strategy covered on the Physical Design page matters so much: a bug caught after tapeout either waits for a metal-only mask respin (touching only a few upper layers, far cheaper) or, in the worst case, requires a full new mask set and another multi-week fabrication cycle.
GDSII & OASIS Format
GDSII (Graphic Data System II) is the long-standing binary stream format for exchanging IC layout data. It has no concept of "layer names" — every shape lives on a numbered layer plus a datatype (both typically 0–255), with the meaning of each number defined externally by a layer-mapping table agreed between the design house and the foundry.
A GDSII/OASIS file is a library of structures (cells); each structure holds geometry (boundary/path/box), text, and references to other structures — single (sref) or arrayed (aref) — which is what lets a design reuse one memory-cell or standard-cell definition millions of times without repeating its geometry.
| Element | What it represents |
|---|---|
| Boundary | A filled polygon — the base geometric shape for most layout features |
| Path | A wire with a defined width, used for wiring-style geometry |
| SREF | Structure reference — instantiates one copy of another cell at a given position/orientation |
| AREF | Array reference — instantiates a regular array of another cell (e.g. a bit-cell array), far more compact than repeating geometry |
| Text | Non-geometric annotation/labels, used for documentation and pin naming, not manufactured |
| Node / Box | Electrical path markers and rectangular geometry placeholders, used less frequently than boundary/path |
As designs scaled, full-chip GDSII databases grew into the hundreds of gigabytes to terabytes, and GDSII's fixed-length integer encoding became a real bottleneck for transfer and load time. OASIS (Open Artwork System Interchange Standard) was developed as a drop-in successor with the same hierarchical structure/cell/element model, but a denser encoding: variable-length integers instead of fixed-length, and explicit repetition compression that recognizes regular patterns (like instantiating a thousand identical polygons) and stores them once with a repeat count instead of per-instance. The result is commonly cited as 5–20× smaller files with correspondingly faster load times, which is why OASIS has increasingly displaced GDSII as the format actually handed to mask shops at advanced nodes, even though "GDSII" remains the everyday shorthand term for "the tapeout file."
Final Signoff Checklist
Signoff isn't one tool run — it's a sequence of independent verification passes, each of which must come back completely clean (or with every violation explicitly waived and signed off by the foundry) before the database is released. The operating principle is blunt: there are no second chances once masks are made.
| Check | What it verifies |
|---|---|
| DRC (Design Rule Check) | Every polygon obeys the foundry's manufacturing rules — minimum width, spacing, area, via enclosure — run with the full foundry runset (e.g. Calibre nmDRC) to zero violations; anything waived needs an explicit foundry sign-off letter |
| LVS (Layout vs. Schematic) | The netlist extracted from the final layout must match the golden gate-level netlist exactly — every transistor, every connection — catching shorts, opens, or connectivity mismatches introduced anywhere in the flow |
| ERC (Electrical Rule Check) | Floating gates, missing ESD protection, unconnected wells/taps, and other electrical hazards not caught by pure geometric DRC or connectivity-only LVS |
| Antenna check | Confirms every net's metal-area-to-gate-area ratio stays below the foundry's per-layer threshold — see Routing for the underlying plasma-charging mechanism and fixes |
| STA across all PVT corners | Setup/hold timing signed off with real extracted parasitics across every functional mode and process/voltage/temperature corner — see Process Corners |
| IR drop / electromigration | Static and dynamic voltage-drop and EM signoff on the fully routed power and signal networks — see EMIR Analysis |
| Density / DFM checks | Metal, poly, and diffusion density windows (for CMP planarity) and other design-for-manufacturability rules — see Fillers & Decaps |
Mask Data Prep: OPC & RET
A clean, signed-off GDSII/OASIS file is not what actually gets printed onto the wafer. Modern lithography prints features far smaller than the wavelength of light used to expose them, and at that scale diffraction and process effects distort sharp polygon corners into rounded, shrunken shapes on real silicon — enough distortion to change a transistor's electrical behavior if left uncorrected.
Optical Proximity Correction pre-compensates the mask geometry so that after diffraction and process effects, the pattern that actually lands on the wafer matches the designer's intended shape.
Optical Proximity Correction (OPC) is the dominant Resolution Enhancement Technique (RET): software analyzes every edge of every polygon and pre-distorts it — adding serifs at corners, biasing line widths, inserting sub-resolution assist features — so that after the light diffracts through the mask and lens system, the resulting printed pattern matches the design's intent rather than the mask's literal shape. Other RETs used alongside OPC include phase-shift masking (using the physics of light interference rather than just blocking/passing light to sharpen edges) and off-axis illumination. This entire step is computationally intensive — full-chip model-based OPC runs are among the most compute-heavy steps in the entire design-to-silicon pipeline, run by the foundry or a mask house (not usually by the design team) using calibrated models of that specific process's optical and etch behavior.
After OPC/RET, the corrected pattern is fractured — decomposed into the specific shape primitives (trapezoids, rectangles) that the mask writer's e-beam or laser system can actually address — producing the mask-writer-ready data that finally goes to the mask shop.
Seal Ring & Scribe Line
Two structures are added at the very edge of the die that have nothing to do with circuit function and everything to do with the die surviving dicing, packaging, and field operation.
The scribe line (also holding process-monitor/PCM structures — see Process Corners) is sacrificed during dicing; the seal ring stops cracks and moisture from that cut from ever reaching the core logic.
Seal ring
A seal ring is a closed loop running around the entire periphery of the die, built from overlapping diffusion, via, and metal layers stacked according to strict foundry design rules — effectively a continuous metal/via wall from front-end to top metal. It serves two protection functions: mechanically, it blocks stress cracks generated during wafer dicing (and later, packaging and field handling) from propagating from the die edge into the active circuit area; and environmentally, its layered oxide/metal/passivation structure resists moisture and contaminant ingress from the exterior. It typically costs roughly 5–8% of die area, which is treated as an accepted tradeoff given the yield and long-term reliability improvement it buys.
Scribe line
The scribe line (also called the "kerf" or dicing street) is the narrow strip of silicon between adjacent die on the wafer, reserved as the physical path the wafer saw or laser dicing tool cuts along to separate individual die. Because this area is destroyed during dicing and never becomes part of any shipped die, it's also where foundries place process-control-monitor (PCM) test structures — the ring-oscillator and test-transistor structures described on the Fabrication page — since they need silicon-level access for measurement but have no reason to consume die area. The seal ring sits just inside the scribe line specifically so it can absorb whatever chipping or micro-cracking the dicing cut itself introduces.
Mask Making & the Foundry Handoff
Once fractured mask data exists for every layer, it goes to a mask shop (sometimes an independent merchant mask house, sometimes an in-house foundry facility) to become physical photomasks — the reticles actually loaded into the lithography scanner during wafer fabrication.
One reticle is produced per mask layer — a full mask set at advanced nodes needs 40–80+ individual masks once multi-patterning layers are counted.
A blank plate — glass or quartz coated with an opaque chrome layer and an anti-reflective coating — is coated with photoresist and directly patterned by an e-beam or laser writer tracing the fractured mask data. The resist is developed and the exposed chrome etched away, leaving the design pattern as clear/opaque regions. The finished mask is inspected and, if minor defects are found, repaired, then a pellicle — a thin, optically transparent membrane stretched across a frame above the mask surface — is mounted; because the pellicle sits above the lithography system's focal plane, any stray particle that lands on it stays out of focus and doesn't print, protecting the mask from the single biggest cause of repeat yield-killing defects.
Mask set cost and MPW shuttles
A full production mask set is one of the largest fixed costs in bringing a chip to market: commonly $500K–$5M+ at mainstream nodes, and reported to reach $3M–$10M+ at 7nm and below once multi-patterning pushes the mask count from roughly 40 up to 80 or more layers. This cost is exactly why the spare-cell ECO strategy (see Floorplanning) and exhaustive pre-tapeout signoff both exist — a caught bug is a rounding error next to a mask respin. For prototyping or low-volume parts, Multi-Project Wafer (MPW) shuttle programs let many unrelated designs share a single wafer and mask set, splitting the cost across all participants — commonly cited as a 70–90% cost reduction versus a dedicated mask set, run on a fixed schedule by foundries across process nodes from legacy 180nm down to advanced nodes.
The handoff package
The GDSII/OASIS file rarely travels alone. A typical foundry handoff bundle also includes the final gate-level netlist and LEF/DEF physical abstracts (for any downstream package-level or multi-die integration work), the final SDC constraints and signed-off timing reports, and the parasitic/timing library corners used for signoff — giving the foundry (and the design team's own archive) everything needed to reproduce or debug the exact signed-off state of the design, not just its final geometry.
Sources
- Appendix C: GDS II Format — Computer Aids for VLSI Design
- GDSII — AnySilicon Semipedia
- OASIS vs GDS: Time to Switch? — Semiconductor Digest
- Going From GDSII to OASIS — EE Times
- Physical Design Signoff — IR Drop, Electromigration & Tapeout Checklist — EcrioniX
- The Ultimate Signoff (Tapeout) Checklist — AnySilicon
- GAN-OPC: Mask Optimization With Lithography-Guided Generative Adversarial Nets — IEEE Xplore
- Performance-Driven OPC for Mask Cost Reduction — IEEE Xplore
- Performance-Based Optical Proximity Correction Methodology — IEEE Xplore
- Advanced Physical Models for Mask Data Verification and Impacts on Physical Layout Synthesis — IEEE Xplore
- Seal ring structure and function, scribe line / dicing street layout — general web research (patent literature: US20080265378A1, diskmfr.com)
- Photomask / reticle production steps, e-beam writing, pellicle mounting — general web research (Heidelberg Instruments, USPTO photomask patents)
- MPW — Multi-Project Wafer — AnySilicon Semipedia
- Multi-Project Wafer (MPW) Guide: Cost, Process & Schedule — VLSI Shuttle