Click any region to open its full page. Dashed green connectors show where a cross-cutting concern feeds into the main flow.
What is VLSI
VLSI is the process of creating an integrated circuit by combining a very large number of transistors into a single chip. It spans the full journey from an idea or specification to a manufactured piece of silicon, and underpins nearly every modern electronic device — from processors and memory to sensors and RF chips.
Modern VLSI design increasingly relies on FinFET and gate-all-around (GAA) transistor structures, 3D/2.5D integration, and AI-driven EDA tools that use machine learning to speed up floorplanning, routing, and signoff.
VLSI Design Flow (RTL to GDSII)
Click any stage to open its section or page. Each stage below also expands on what happens in that phase.
Specification
Define functional, performance, power, and area requirements for the chip — see Logic Synthesis.
RTL Design
Describe logic behavior in Verilog/VHDL at the register-transfer level — see Logic Synthesis.
Functional Verification
Simulate and verify the RTL matches the intended specification before synthesis — see Logic Synthesis.
Logic Synthesis
Translate RTL into a gate-level netlist mapped to a standard cell library — see Logic Synthesis.
Floorplanning
Place macros, define core/die area, and plan power straps and I/O — see Physical Design.
Power Planning
Build the power delivery network (PDN) — rings, straps, and rails — see Power Integrity.
Clock Tree Synthesis
Build balanced clock distribution to minimize skew and latency — see Physical Design.
Routing
Connect all placed cells with metal interconnect across routing layers — see Physical Design.
Signoff (STA, DRC, LVS)
Static timing analysis (see Static Timing Analysis), IR drop/EM checks, design rule and layout-vs-schematic checks — see Physical Design.
Tapeout / GDSII
Final signoff, GDSII/OASIS export, mask data prep, and handoff to the foundry — see Tapeout / GDSII.
Fabrication
Wafer processing, process corners, yield, and post-silicon bring-up & ATPG — see Fabrication.
Topics
Deep-dive subpages under VLSI. Click a ready topic to open it.
Power Integrity
PDN, IR drop, decoupling capacitors, electromigration, and power signoff.
Static Timing Analysis
Setup/hold analysis, timing path types, clock uncertainty & CRPR, timing exceptions, and MCMM signoff.
Physical Design
Floorplanning (tap/boundary/spare cells), placement & SDC uncertainty, CTS in depth, routing checks, fillers/decaps, and interface timing.
DFT
Scan & ATPG, fault models, LBIST/JTAG/IDDQ, and a deep dive on MBIST & memory testing.
Low Power Design
Multi-Vt cell selection, power gating architecture (header/footer, fine/coarse-grain, rush current), adaptive body biasing, and DVFS/AVS.
Logic Synthesis
Stages 01–04: Specification, RTL Design, Functional Verification, and RTL-to-gate synthesis.
Fabrication
Stage 12: wafer processing, process corners, on-chip variation, yield, and post-silicon ATPG.
Tapeout / GDSII
Stage 11: GDSII/OASIS format, final signoff checklist, mask data prep (OPC/RET), seal ring/scribe line, and mask making.
Key Terms
| Term | Meaning |
|---|---|
| RTL | Register-Transfer Level — hardware description of logic behavior (e.g. Verilog, VHDL) |
| GDSII | Standard file format for final chip layout data sent to the foundry |
| PDN | Power Delivery Network — the on-chip structure distributing voltage/current to logic |
| STA | Static Timing Analysis — verifies timing without simulation vectors |
| DRC / LVS | Design Rule Check / Layout-vs-Schematic — physical and electrical verification |
| FinFET / GAA | Modern 3D transistor structures used at advanced process nodes |